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ver.8 NJW1320 -1- wide band video switch with i 2 c bus general description package outline the NJW1320 is a wide band video switch with i 2 c bus.the NJW1320 includes switch of 4-input 3-output and 6db amplifier. it is suitable for y, pb, and pr signal because frequency range is 50mhz.the NJW1320 includes external logic control terminals and external logic discernment terminals. the NJW1320 is suitable for ptv, dtv, pdp and other high quality av systems. features operating voltage 9.0v 4-input 3-output 3-circuits (y, pb, and pr signal) wide frequency range 0db at 50mhz typ. internal 6db amplifier (selectable bypass or 6db) external logic discernment terminal external logic control terminal selectable slave address power save circuit i 2 c bus control bi-cmos technology package outline qfp48 block diagram NJW1320fp1 6db 6db 6db 6db 6db 6db 6db 6db 6db i 2 c bus y in1 y in2 y in3 y in4 pb in1 pb in2 pb in3 pb in4 pr in1 pr in2 pr in3 pr in4 y out1 y out2 y out3 pb out1 pb out2 pb out3 pr out1 pr out2 pr out3 address sda scl vcc gnd aux 0 aux 1 aux 2 aux 3 port 0 port 1 port 2 port 3 vref bias dgnd
- 2 - NJW1320 pin configuration 1. pr in3 15. port3 25. aux0 39. y in4 2. gnd 16. port2 26. aux1 40. gnd 3. y in2 17. port1 27. pr out3 41. pb in4 4. gnd 18. port0 28. pb out3 42. gnd 5. pb in2 19. vref 29. y out3 43. pr in4 6. gnd 20. gnd 30. aux2 44. v+ 7. pr in2 21. dgnd 31. pr out2 45. y in3 8. gnd 22. scl 32. pb out2 46. gnd 9. y in1 23. sda 33. y out2 47. pb in3 10. gnd 24. adr 34. aux3 48. gnd 11. pb in1 35. pr out1 12. gnd 36. pb out1 13. pr in1 37. y out1 14. gnd 38. gnd pr in3 pb in 2 pr in 2 gnd gnd gnd gnd gnd gnd y in 1 gnd pr in1 pb in1 port3 port2 port1 port0 vref gnd dgnd scl sda a d r 1 14 38 25 39 24 48 15 gnd pb in3 gnd y in3 v+ pr in4 gnd pb in4 gnd y in4 y in 2 a ux0 a ux1 pr out3 pb out3 y out3 aux2 pr out2 pb out2 y out2 aux3 pr out1 pb out1 y out1 gnd
-3- NJW1320 absolute maximum ratings (ta=25 c) parameter symbol ratings unit supply voltage v + 12.0 v power dissipation p d 1875(note) mw operating temperature range topr -25 to +75 c storage temperature range tstg -40 to +150 c (note) at on a board of eia/jedec specification. (76.2 114.3 1.6mm two layers, fr-4) electrical characteristics (v + =9.0v, r l =10k ? , ta=25 c) video parameter symbol test condition min. typ. max. unit operating voltage v + 8.0 9.0 10.0 v operating current i cc no signal - 70 100 ma maximum output voltage vom f=100khz, thd=1% 2.0 2.5 - vp-p voltage gain 1 gv1 vin=100khz, 1.0vp-p sin signal 6db mode 6.0 6.4 6.8 db voltage gain 2 gv2 vin=100khz, 1.0vp-p sin signal bypass mode -0.5 0.0 0.5 db frequency characteristic 1 gf1 vin=50mhz / 100khz, 1.0vp-p sin signal 6db mode - 0 - db frequency characteristic 2 gf2 vin=50mhz / 100khz, 1.0vp-p sin signal bypass mode - 0 - db cross talk 1 ctb1 vin=4.43mhz,1.0vp-p sin signal - -60 -50 db cross talk 2 ctb2 vin=30mhz,1.0vp-p sin signal - -40 - db differential gain dg vin=1.0vp-p 10step video signal - 0.3 - % differential phase dp vin=1.0vp-p 10step video signal - 0.3 - deg s/n snv vin=1.0vp-p,100% white video signal - 65 - db port, aux parameter symbol test condition min. typ. max. unit port input voltage h v pth 3.5 - 5.5 v port input voltage m v ptm 1.4 - 2.4 v pory input voltage l v ptl 0 - 0.8 v aux output voltage h v auxh 3.5 - 5.5 v aux output voltage m v auxm 1.4 - 2.4 v aux output voltage l v auxl 0 - 0.8 v adr input voltage h v adrh 3.5 - 5.0 v adr input voltage l v adrl 0 - 1.0 v
- 4 - NJW1320 sda scl t f t hd:st a t low t r t hd:dat t high t f t su:dat s t su:sta t hd:st a t sp t su:sto sr t r t buf p s i 2 c bus block characteristics (sda,scl) i 2 c bus load conditions standard mode: pull up resistance 4k ? (connected to +5v), load capacitance 200pf (connected to gnd) parameter symbol min typ max unit low level input voltage v il 0.0 - 1.5 v high level input voltage v ih 2.7 - 5.5 v low level output voltage (3ma at sda pin) v ol 0 - 0.4 v output fall time from v ihmin to v ilmax with a bus capacitancefrom 10pf to 400pf t of - - 250 ns input current each i/o pin with an input voltage between 0.1 and 0.9v ddmax i i -10 - 10 a capacitance for each i/o pin c i - - 10 pf scl clock frequency f scl - - 100 khz data transfer start minimum waiting time t hd:sta 4.0 - - s low level clock pulse width t low 4.7 - - s high level clock pulse width t high 4.0 - - s minimum start preparation waiting time t su:sta 4.7 - - s minimum data hold time t hd:dat 0 - - s minimum data preparation time t su:dat 250 - - ns rise time t r - - 1000 ns fall time t f - - 300 ns minimum stop preparation waiting time t su:sto 4.0 - - s data change minimum waiting time t buf 4.7 - - s capacitive load for each bus line c b - - 400 pf noise margin at the low level v nl 0.5 - - v noise margin at the high level v nh 1 - - v c b ; total capacitance of one bus line in pf.
-5- NJW1320 terminal description no. symbol function equivalent circuit voltage 9 11 13 3 5 7 45 47 1 39 41 43 y1 in pb1 in pr1 in y2 in pb2 in pr2 in y3 in pb3 in pr3 in y4 in pb4 in pr4 in component signal input terminal 4.4v 18 17 16 15 port0 port1 port2 port3 logic input terminal - 19 vref reference voltage terminal 5.0v 2 4 6 8 10 12 14 20 38 40 42 46 48 gnd ground terminal - 21 dgnd ground terminal - v + 100 ? 150k ? v + y1 in y2 in y3 in y4 in pb1 in pb2 in pb3 in pb4 in pr1 in pr2 in pr3 in v + 100k ? 66 ? port0 port1 port2 port3 v + v + 66 ? vref v + v + v + 48k ?
- 6 - NJW1320 no. symbol function equivalent circuit voltage 22 23 scl sda i 2 c clock terminal i 2 c data terminal - 24 adr slave address setting terminal - 25 26 27 28 aux0 aux1 aux2 aux3 auxiliary 3 values voltage output terminal 0v 1.9v 5.0v 37 34 31 36 33 30 35 32 29 y1 out y2 out y3 out pb1 out pb2 out pb3 out pr1 out pr2 out pr3 out component signal output terminal 3.0v 44 v+ supply voltage terminal - y1 out y2 out y3 out pb1 out pb2 out pb3 out pr1 out pr2 out pr3 out v + v + 50 ? 66 ? aux0 aux1 aux2 aux3 v + v + v + 1k ? vref 66 ? adr v + v + 80k ? scl sda
-7- NJW1320 definition of i 2 c register ? ? ? ? i 2 c bus format msb lsb msb lsb msb lsb s slave address a data a data a p 1bit 8bit 1bit 8bit 1bit 8bit 1bit 1bit s: starting term a: acknowledge bit p: ending term ? ? ? ? slave address r/w: set the write mode or read mode. adr : set the slave address by ?adr? terminal. slave address hex msb lsb - 1 0 0 0 0 0 adr r/w - r/w = 0 : write mode, adr = 0/1 - 1 0 0 1 0 1 0 0 94(h) 1 0 0 1 0 1 1 0 96(h) r/w = 1 : read mode, adr = 0/1 - 1 0 0 1 0 1 0 1 95(h) 1 0 0 1 0 1 1 1 97(h) ? ? ? ? control register table < write mode > bit no. d7 d6 d5 d4 d3 d2 d1 d0 data1 ps2 ps3 out1 out2 data2 out3 ? data3 aux0 aux1 aux2 aux3 ? : don?t care < read mode > bit no. d7 d6 d5 d4 d3 d2 d1 d0 data port0 port1 port2 port3 ? ? ? ? control register default value control register default value is all ?0?. bit no. d7 d6 d5 d4 d3 d2 d1 d0 data1 0 0 0 0 0 0 0 0 data2 0 0 0 0 0 0 0 0 data3 0 0 0 0 0 0 0 0
- 8 - NJW1320 ? instruction code ? ? ? ? power save, output setting bit no. d7 d6 d5 d4 d3 d2 d1 d0 data1 ps2 ps3 out1 out2 data2 out3 ? ? : don?t care ? ? ? ? ps2, ps3: power save setting power save d7 d6 out1 on out2 on out3 on 0 0 out1 on out2 on out3 off 0 1 out1 on out2 off out3 on 1 0 out1 on out2 off out3 off 1 1 on: power save off, off: power save on ? ? ? ? out1: output 1 setting output 1 d5 d4 yin1 pbin1 prin1 0 0 yin2 pbin2 prin2 0 1 yin3 pbin3 prin3 1 0 yin4 pbin4 prin4 1 1 ? ? ? ? out2: output 2 setting output 2 d2 d1 yin1 pbin1 prin1 0 0 yin2 pbin2 prin2 0 1 yin3 pbin3 prin3 1 0 yin4 pbin4 prin4 1 1 ? ? ? ? out3: output 3 setting output 3 d7 d6 yin1 pbin1 prin1 0 0 yin2 pbin2 prin2 0 1 yin3 pbin3 prin3 1 0 yin4 pbin4 prin4 1 1 gain d3 6db 0 0db 1 gain d0 6db 0 0db 1 gain d5 6db 0 0db 1
-9- NJW1320 ? ? ? ? aux: auxiliary setting bit select address d7 d6 d5 d4 d3 d2 d1 d0 data3 aux0 aux1 aux2 aux3 aux0 d7 d6 l 0 0 m 0 1 h 1 1 aux1 d5 d4 l 0 0 m 0 1 h 1 1 aux2 d3 d2 l 0 0 m 0 1 h 1 1 aux3 d1 d0 l 0 0 m 0 1 h 1 1 ? ? ? ? port: port setting bit select address d7 d6 d5 d4 d3 d2 d1 d0 data port0 port1 port2 port3 port0 d7 d6 open 0 0 l 0 0 m 0 1 h 1 1 port1 d5 d4 open 0 0 l 0 0 m 0 1 h 1 1 port2 d3 d2 open 0 0 l 0 0 m 0 1 h 1 1 port3 d1 d0 open 0 0 l 0 0 m 0 1 h 1 1
- 10 - NJW1320 test circuit 50 ? /75 ? 1uf 0.1uf c1 c2 r1 + 100uf + 0.1uf c44 c45 50 ? /75 ? 1uf 0.1uf c3 c4 r2 + 50 ? /75 ? 1uf 0.1uf c7 c8 r4 + 1uf + 50 ? /75 ? 1uf + 0.1uf c9 c10 r5 r6 1uf + 0.1uf c11 c12 50 ? /75 ? r7 1uf + 0.1uf c13 c14 50 ? /75 ? r8 1uf + 0.1uf c15 c16 50 ? /75 ? r9 1uf + 0.1uf c17 c18 50 ? /75 ? r10 1uf + 0.1uf c19 c20 50 ? /75 ? r11 1uf + 0.1uf c21 c22 50 ? /75 ? r12 1uf + 0.1uf c23 c24 50 ? /75 ? 10k ? 10uf + 0.1uf c25 c26 r13 10k ? 10uf + 0.1uf c27 c28 r14 10k ? 10uf + 0.1uf c29 c30 r15 10k ? r47 10uf + 0.1uf c31 c32 r16 10k ? 10uf + 0.1uf c33 c34 r17 10k ? 10uf + 0.1uf c35 c36 r18 10k ? 10uf + 0.1uf c37 c38 r19 10k ? 10uf + 0.1uf c39 c40 r20 10k ? 10uf + 0.1uf c41 c42 r21 10k ? r48 10k ? r49 10k ? r50 c43 y4 in pb4 in y3 in pb3 in pr3 in y2 in pb2 in pr2 in y1 in pb1 in pr1 in port0 port2 port1 port3 sd a adr scl aux0 aux1 pr3 out aux3 aux2 pb3 out y3 out pr2 out pb2 out y2 out pr1 out pb1 out v+ NJW1320 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 1011121314 y1 out pr4 in 50 ? /75 ? 1uf 0.1uf c5 c6 r3 + 10k ?
-11- NJW1320 applacation circuit addition of r26-r34 improves the through rate in high frequency. resistance turns into a reference value. 50 ? /75 ? 1uf 0.1uf c1 c2 r1 + 100uf + 0.1uf c44 c45 50 ? /75 ? 1uf 0.1uf c3 c4 r2 + 50 ? /75 ? 1uf 0.1uf c7 c8 r4 + 1uf + 50 ? /75 ? 1uf + 0.1uf c9 c10 r5 r6 1uf + 0.1uf c11 c12 50 ? /75 ? r7 1uf + 0.1uf c13 c14 50 ? /75 ? r8 1uf + 0.1uf c15 c16 50 ? /75 ? r9 1uf + 0.1uf c17 c18 50 ? /75 ? r10 1uf + 0.1uf c19 c20 50 ? /75 ? r11 1uf + 0.1uf c21 c22 50 ? /75 ? r12 1uf + 0.1uf c23 c24 50 ? /75 ? 10k ? 10uf + 0.1uf c25 c26 r13 10k ? 10uf + 0.1uf c27 c28 r14 10k ? 10uf + 0.1uf c29 c30 r15 10k ? r47 10uf + 0.1uf c31 c32 r16 10k ? 10uf + 0.1uf c33 c34 r17 10k ? 10uf + 0.1uf c35 c36 r18 10k ? 10uf + 0.1uf c37 c38 r19 10k ? 10uf + 0.1uf c39 c40 r20 10k ? 10uf + 0.1uf c41 c42 r21 10k ? r48 10k ? r49 10k ? r50 c43 y4 in pb4 in y3 in pb3 in pr3 in y2 in pb2 in pr2 in y1 in pb1 in pr1 in port0 port2 port1 port3 sd a a dr scl a ux0 a ux1 pr3 out a ux3 a ux2 pb3 out y3 out pr2 out pb2 out y2 out pr1 out pb1 out v+ NJW1320 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 1011121314 y1 out pr4 in 50 ? /75 ? 1uf 0.1uf c5 c6 r3 + 10k ? r26 r27 r28 r29 r30 r31 r32 r33 r34 1.5k ? 1.5k ? 1.5k ? 1.5k ? 1.5k ? 1.5k ? 1.5k ? 1.5k ? 1.5k ?
- 12 - NJW1320 note please ground all of 2, 4, 6, 8, 10, 12, 14, 20, 21, 38, 40, 42, 46, and 48pin. when the power supply voltage is not impressing, please do not impress voltage to the adl terminal. typical characteristics [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. -40 -30 -20 -10 0.0 10 100 10 3 1 10 6 10 10 6 100 10 6 voltage gain vs. frequency gain (db) frequency (hz) signal power = +4dbm 0db mode 6db mode

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